1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and, more specifically, to such an LCD device as having an upper-level pattern such as a wiring layer crossing a lower-level pattern such as a semiconductor layer.
2. Description of the Related Art
While an LCD device is classified roughly into an active type and a passive type, the active type LCD device has been recently widely employed. In the active type, an active element such as a transistor and a metal-insulator-metal (M IM) element is used as a switching element for driving an liquid crystal cell. As such a transistor, a thin film transistor (TFT) of the inverted staggered type is usually used.
The TFT of the inverted staggered type includes basically a gate electrode formed on a substrate such as glass, a semiconductor layer formed on a gate insulating film covering the gate electrode, and source and drain electrodes which are in an ohmic contact with the semiconductor layer. The source (drain) electrode is connected to a signal line to which image data is supplied, and a drain (source) electrode is connected to a pixel electrode of a pixel (picture element). The gate electrode is connected to a scan line to which a scan signal is supplied to render the TFT conductive and non-conductive.
As another TFT, a staggered type is known in which a semiconductor layer and source/drain electrodes are formed in lower level than a gate insulating film, and a gate electrode is formed on the gate insulating layer.
In case of performing a display in X and Y axes plane, the liquid crystal pixels and thus the switching transistors are arranged in a matrix. Therefore, a plurality of scan lines are formed in parallel to each other in the X direction, and a plurality of signal lines are formed in parallel to each other in the Y direction, each TFT being thus disposed on the different one of the intersections of the scan and signal lines. As a result, the scan and signal lines cross to each other with an electrical isolation between the scan and signal lines. In the LCD device employing the inverted staggered type, the scan and signal lines are formed respectively as a lower-level wiring layer and an upper-level wiring layer. In the staggered type, on the other hand, the scan and signal lines are formed respectively as an upper-level wiring layer and a lower-level wiring layer. The electrical isolation between the scan and signal lines is attained by utilizing the gate insulating layer, as is apparent from the above. In order to avoid the short-circuit between the crossing lines that may occur due to pinhole(s) formed in the gate insulating layer, an island semiconductor layer, which is patterned simultaneously with forming the semiconductor layer functioning as the channel region of the TFT, intervenes between the scan and signal lines.
Thus, the upper-level wiring layer crosses the edge of the lower-level pattern such as the island semiconductor layer. The upper-level wiring layer is formed by depositing a wiring material over the entire surface of the substrate and then patterning the wiring material by selective-etching process using the photolithography. At this time, due to the lowering in adhesive strength of the wiring material to the lower-level pattern that are caused by the step at the edge of the lower-level pattern, the etchant used in the selective-etching process soaks between the lower-level pattern and the wiring material along the edge of the lower-level pattern to remove desired portions of the wiring material. At the worst case, the upper-level wiring layer is broken down. Such phenomena may takes place at the crossing portions of the source/drain electrodes and the semiconductor channel layer of the TFT.
In order to solve the above problems, therefore, the Japanese Laid-Open (Kokai) Patent Publication Hei 2-20830 discloses providing, in a plane view, at least one protrusion and/or indentation at the edge of the crossing portion of the lower-level pattern to the upper-level portion. This countermeasure is to make large the effective length of the crossing edge of the lower-level pattern to the upper-level pattern by the protrusion and/or indentation. With such construction, even if the etchant soaks between the upper-level and lower-level pattern, the breaking-down of the upper-level pattern is prevented.
More specifically, as the partial plane view of the LCD device according to the above publication is shown in FIG. 5, this device employs the TFT 1 of the inverted staggered type. This TFT 1 thus includes scan wiring layer 2, an intrinsic amorphous silicon (a-Si) layer 3a as a semiconductor layer that is formed on a gate insulating layer covering the scan line 2, a protective layer 3b formed thereover to protect the channel region of the a-Si layer 3, n+ (high-conductivity) amorphous silicon (n-a-Si) layers 3c formed on the a-Si layer 3 to present an ohmic contact with electrodes, source and drain electrodes 4a and 4b formed on the n-a-Si layers 3c, and an pixel (picture element) electrode 5 connected to the electrode 4b. In this device, apart of the scan line also functions as agate electrode, and the electrode 4a is branched from a signal line 4. At the crossing portion of the scan and signal lines 2 and 4, for the reasons described above, there are provided in addition to the gate insulating film, an island a-Si layer 3a, an island n-a-Si layer 3c and a channel protective layer 3b. 
In order to prevent the breaking-down of the signal line 4 (the upper pattern), each of the a-Si layers 3a and 3c is patterned such that its edge, over which the signal line 4 or the electrodes 4a and 4b cross, becomes concavo-convex in plane view by providing two protrusions. By this patterning, the length of the crossing edge line of each a-Si layer 3 to the wiring line 4 or the electrodes 4a and 4b is made larger. As a result, even if the etchant for selectively patterning the wiring line 4 and the electrodes 4a and 4b soaks along the such crossing edge line, the braking-down of the line 4 and the electrodes 4a and 4b is prevented.
The LCD display is requested not only solving the problems in its manufacturing process but also enhancing its display quality. One of the issues to be enhanced in the display quality is the so-called aperture ratio. That is, it is requested to increase the aperture ratio. This request is achieved by make the areas of the light impermissible layers as small as possible. To this end, in the LCD device shown in FIG. 5, the wiring layer such as the signal line 4 and the scan line 2 is required to be made small in its width to thereby increase the area of the pixel electrode 5 surrounded by these wiring layers 4 and 2.
It has been, however, recognized by the inventors that the following serious problems caused by lowering the width of the signal line 4 (upper wiring layer) of the LCD device shown in FIG. 5 for the purpose of increasing the aperture ratio. Specifically, the signal line 4 is patterned by the selective-etching method performed on the wiring material layer formed over the entire surface of the substrate, and to do the selective-etching, it is required to form a mask layer on the wiring material. The mask layer is usually formed by projecting a wiring pattern, which is provided on a photo-mask, on a photoresist layer formed on the wiring material layer. At this time, it is unavoidable that the deviation in alignment between the photo-mask and the LCD substrate occurs. As a result, the signal line 4 is not formed in the designed center location, but is actually formed with some deviation in the up-and-down and/or left-and right direction from the designed center location. For this reason, if the width of the signal line 4 is made small for the high aperture ratio, such a case may occur that one of the side edges defining the width of the signal line 4 (in FIG. 5, the side edge of the line 4 in the Y axis direction) is substantively coincident in plane view with the edge of one protrusion of the a-Si layer 3 which edge is parallel to the side edge of the signal line 4. Although two protrusions are provided in the LCD device shown in FIG. 5, it is possible to provide only one protrusion (or indentation). Even in such case, the above state easily occurs, because there are formed, between the pair of side edges defining the width of the signal line 4, two edges of the a-Si layer protrusion (or indentation) that are parallel to the pair of side edges.
FIG. 6 illustrates a sectional view along the line Axe2x80x94A of FIG. 5 in the case where the signal line 4 has been actually formed with the leftward deviation from the designed center position. As is apparent therefrom, by the side edge of the signal line 4 almost overlapping with the side edge of the a-Si protrusion layer, there is formed a sharp and relatively high step 50 at their overlapping portion. It is noted that the reference numeral 10 indicates the gate insulating film. In order to complete the LCD device, the protective layer 8 and an orientation layer (not shown) are there after formed, followed by injecting a liquid crystal layer 9. It is hard to completely cover the above step 50 with the protective and orientation layers, so that some cracks are left in the portions of these layers corresponding to the step 50. The liquid crystal is thereby in contact with the signal line 4. Upon operation under such condition, such an electrochemical reaction occurs that the reacted metals flowing to the liquid crystal layer 9. As a result, the display uniformity is deteriorated and/or some displays stains are made.
It will be understood that the above problems may occur also in the LCD device in which the upper wiring layer such as a signal line is not so small in width as being not required to have high aperture ratio, because the phenomenon causing the above problems is dependent on the pattern deviation amount and/or the number or size of the a-Si protrusions (or indentations).
The crossing structures of the upper-level and lower-level patterns exist in a LCD device of the in-plane switching (IPS) type. If the resistance value of the liquid crystal is low that the electric chemical reaction occurs easily. Then, the LCD device of the IPS type generally uses the liquid crystal of the lower resistance value than the LCD device of the TN type. Accordingly, the above problems of the LCD device of the IPS type are serious problems more than the LCD device of the TN type.
It is therefore an object of the present invention to provide a more improved liquid crystal display device.
It is another object of the present invention to provide a liquid crystal display device having an improved crossing structure between an lower-level pattern and an upper-level pattern.
It is still another object of the present invention to provide a liquid crystal display device having such a structure that prevents the breaking-down of an upper-level pattern that may occur at the crossing portion thereof to a lower-level pattern and that further solves a problem that the lower-level and upper-level patterns overlap with each other in the different direction.
A liquid crystal display device according to the present invention includes a lower-level pattern and an upper-level pattern that crosses the lower-level pattern and has its width defined by a pair of side edges, so that such crossing structure has two, first and second, crossing points. At the first crossing point, one the pair of side edges of the upper-level pattern crosses a certain edge of the lower-level pattern, and at the second crossing point the other of the pair of side edges crosses the same edge of the lower-level pattern. Moreover, the above edge of the lower-level pattern having the first and second crossing points is formed such that a first extension line extending from the first crossing point in the widthwise direction of the upper-level pattern does not overlap with a second extension line extending from the second crossing point in the widthwise direction of the upper-level pattern.
In the above construction, the edge of the lower-level pattern that crosses the upper-level pattern is formed or patterned to have the first crossing point as a beginning point and the second crossing point as an ending point on the condition that the first extension line extending from the first crossing (the beginning) point does not overlap with the second extension line extending from the second crossing (the ending) point. In order to for the edge of the lower-level pattern to have such beginning and ending points, the edge line running from the beginning point can reach the ending point while bending twice between the beginning and ending points. In that case, if each of the bending angles is set to be a right angle, the edge of the lower-level pattern is composed of three line segments. This means that the central line segment becomes parallel to the side edges defining the width of the upper-level pattern, and the remaining two line segments cross the side edges of the upper-level pattern to constitute the first and second crossing points, respectively. Thus, it becomes possible that the lower-level pattern has only one line segment that is in parallel to the pairs of side edges defining the width of the upper-level pattern.
On the other hand, in the LCD device shown in FIG. 5, the pattern of the edge of the lower-level pattern (the a-Si layer 3) crossing the upper-level pattern (the signal line 4) is defined such that two crossing points, at which the pair of side edges defining the width of the upper-level pattern intersecting the edge of the lower-level pattern, has the same Y-coordinates as each other. In other words, the extension line extending form the first crossing point in the widthwise direction of the upper-level pattern overlaps with the extension line extending from the second crossing point in the widthwise direction of upper-level pattern. For this reason, the provision of the at least one protrusion (or indentation) of the lower-level pattern results in formation of two line segments at minimum in the edge of the lower-level pattern, which are in parallel to the side edges defining the width of the upper-level pattern.
In the present invention, it is possible to form the lower-level pattern with such an edge that has only one line segment which is in parallel to the side edges of the upper-level pattern. Accordingly, even if the pattern deviation (mask alignment deviation) occurs during the formation of the upper-level pattern to shift the location thereof, the upper-level pattern can be free from such situation wherein the one of the side edges of the upper-level pattern overlaps with such an edge of the lower-level pattern that is in parallel to the side edges of the upper-level pattern. Moreover, the edge of the lower-level pattern, which crosses the upper-level pattern, consists of three line segments in the above description, so that the breaking-down of the upper-level pattern can be also prevented.
In the crossing structure according to another scope of the present invention, the lower-level pattern is formed or patterned to have its edge that includes a first portion extending in a first direction intersecting a second direction in which an upper-level pattern runs, a second portion extending in the first direction but being different in position in the second direction from the first portion, and a third portion exiting between the first and second portions to form the connection between the first and second portions, and the upper-level pattern if formed such a pair of side edges defining the width thereof cross the first and second portions of the edge of the lower-level pattern, respectively.
The present invention is preferably applied to an LCD device of the active type, in which a plurality of TFTs are arranged in matrix to drive an corresponding one liquid crystal cells (pixels). In that case, the crossing structure according to the present invention is used in each of the crossing portions of scan and signal lines. In particular, in case of using the TFT of the inverted staggered type, the lower-level pattern is an island semiconductor layer and the upper-level pattern is a signal (data ) lines. As a display mode, which of the twisted nematic (TN) mode, the IPS mode, a vertical alignment (VA) mode, or any mode may be applied.